This application is related to Japanese application JP 2002-054367 filed on Feb. 28, 2002, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor memory and, more specifically, to a semiconductor memory which, if having a defective memory cell therein, can be used as a memory having a smaller memory capacity than its original capacity without using an area in which the defective memory cell is present.
2. Description of the Related Art
An exemplary semiconductor memory of the aforesaid type is disclosed in Japanese Unexamined Patent Publication No. SHO 59 (1984)-40392. The construction of this semiconductor memory will be described with reference to FIG. 6.
FIG. 6 illustrates an address data input section of the semiconductor memory. In FIG. 6, there are shown address input terminals (hereinafter referred to as xe2x80x9cpinsxe2x80x9d) 110 to 11n for receiving plural address data bits A0 to An respectively supplied thereto, and address buffers 120 to 12n provided in one-to-one correspondence with the respective pins 110 to 11n for outputting address data pairs A0, A0 (A0: the inverse of A0), A1, A1, . . . , and AnAn each having a complementary relationship on the basis of the address data bits A0 to An.
Enhancement-mode MOSFETs 130 to 13n are respectively inserted between the pins 110 to 11n and the corresponding address buffers 120 to 12n with drains and sources thereof connected to the pins 110 to 11n and the address buffers 120 to 12n. Further, enhancement-mode MOSFETs 140 to 14nxe2x88x921 are respectively inserted between the pins 110 to 11nxe2x88x921 and input terminals of the address buffers 121 to 12n at one-bit higher hierarchical levels with drains and sources thereof connected to the pins 110 to 11nxe2x88x921 and the address buffers 121 to 12n.
Gates of the MOSFETs 130 to 13n are connected via a common interconnection line 15, while gates of the MOSFETs 140 to 14nxe2x88x921 are connected via a common interconnection line 16.
An upper end of the interconnection line 15 as seen in FIG. 6 is connected to a positive power supply voltage VDD via a depletion-mode MOSFET 17. A gate of the MOSFET 17 is also connected to the power supply voltage VDD. A lower end of the interconnection line 15 as seen in FIG. 6 is connected to a reference power supply voltage VSS via a depletion-mode MOSFET 18. A gate of the MOSFET 18 is also connected to the power supply voltage VSS. The MOSFETs 17, 18 are each properly dimensioned so that the interconnection line 15 is kept at a logic xe2x80x9c1xe2x80x9d level.
Where a logic circuit is employed which is operative on the basis of a 0-V signal defined as an L-level signal (low level signal) and a 5-V signal defined as an H-level signal (high level signal), for example, a logic xe2x80x9c0xe2x80x9d level and a logic xe2x80x9c1xe2x80x9d level herein mean the L-level signal and the H-level signal, respectively.
An upper end of the interconnection line 16 as seen in FIG. 6 is connected to the reference power supply voltage VSS via a depletion-mode MOSFET 19. A gate of the MOSFET 19 is also connected to the power supply voltage VSS. A lower end of the interconnection line 16 as seen in FIG. 6 is connected to the power supply voltage VDD via a depletion-mode MOSFET 20. A gate of the MOSFET 20 is also connected to the power supply voltage VDD. The MOSFETs 19, 20 are each properly dimensioned so that the interconnection line 16 is kept at the logic xe2x80x9c0xe2x80x9d level.
FIGS. 7(a) and 7(b) illustrate address fixing circuits provided at address data output terminals of each of the address buffers 120 to 12n. The address fixing circuits are adapted to fix the output data Ai, Ai at given levels on the basis of control signals F11, F12 irrespective of the address data applied to the output terminals. As shown in FIGS. 7(a) and 7(b), the address fixing circuits respectively include a pair of enhancement-mode MOSFETs 31, 32 and a pair of enhancement-mode MOSFETs 33, 34.
The address data input section of the semiconductor memory is operative in the following manner. In a normal operation, all the MOSFETs 130 to 13n are in an ON state, and all the MOSFETs 140 to 14nxe2x88x921 are in an OFF state. Therefore, the address data bits A0 to An respectively supplied to the pins 110 to 11n are transferred to the input terminals of the corresponding address buffers 120 to 12n via the MOSFETs 130 to 13n the ON state. In this case, memory cells (not shown) of the semiconductor memory are all addressable on the basis of the address data bits A0 to An. That is, none of the memory cells of the semiconductor memory is defective.
FIG. 5 illustrates a memory cell array. It is assumed that a left half of the memory cell array is designated by an address data value An=0 and a right half of the memory cell array is designated by an address data value An=1. An explanation will be given to a case where a defective memory cell occurs in an area X in FIG. 5, i.e., in a memory area designated by the address data value An=0.
In this case, the memory area (area X) designated by the address data value An=0 is not used. To this end, the control signals F11 to be applied to the address fixing circuits (FIGS. 7(a) and 7(b)) in the address buffer 12n are set at the xe2x80x9c1xe2x80x9d level. As a result, the address data value An is set at An=1 irrespective of the value of the address data bit supplied to the pin 11n, so that the memory area designated by the address data value An=0 is not selected.
Therefore, even if the defective memory cell occurs in the area designated by the address data value An=0 in the semiconductor memory, the semiconductor memory can be used as a memory having a memory capacity one half its original capacity without using the bin 11n at the highest hierarchical level.
Next, an explanation will be given to a case where defective memory cells occur in areas W1, W3 in FIG. 5, i.e., memory areas designated by an address data value Anxe2x88x921=0.
In this case, the memory areas (areas W1, W3) designated by the address data value Anxe2x88x921=0 are not used. To this end, the control signals F11 to be applied to the address fixing circuits (FIGS. 7(a) and 7(b)) in the address buffer 12nxe2x88x921 are set at the xe2x80x9c1xe2x80x9d level. As a result, the address data value Anxe2x88x921 is set at Anxe2x88x921=1 irrespective of the value of the address data bit supplied to the pin 11nxe2x88x921, so that the memory areas designated by the address data value Anxe2x88x921=0 are not selected.
In this case, the MOSFETs 130 to 13nxe2x88x922 and 14nxe2x88x921 are set in the ON state, and the MOSFETs 140 to 14nxe2x88x922, 13nxe2x88x921 and 13n are set in the OFF state for shifting a transfer line for the address data bit Anxe2x88x921.
This setting is achieved by isolating the interconnection lines 15 and 16 from the MOSFETs 17 and 19, respectively. More specifically, the interconnection lines 15, 16 are composed of polycrystalline silicon or aluminum. The interconnection line 15 is fused off between gate junctions of the MOSFETs 13nxe2x88x922 and 13nxe2x88x921 and the interconnection line 16 is fused off between gate junctions of the MOSFETs 14nxe2x88x922 and 14nxe2x88x921 by laser radiation.
Thus, a part of the interconnection line 15 between the gate of the MOSFET 13nxe2x88x921 and the MOSFET 18 which has been kept at the logic xe2x80x9c1xe2x80x9d level is set at the logic xe2x80x9c0xe2x80x9d level, so that the MOSFETs 13nxe2x88x921, 13n are turned off. Further, a part of the interconnection line 16 between the gate of the MOSFET 14nxe2x88x921 and the MOSFET 20 which has been kept at the logic xe2x80x9c0xe2x80x9d level is set at the logic xe2x80x9c1xe2x80x9d level, so that the MOSFET 14nxe2x88x921 is turned on.
By this operation, the transfer line for the address data bit Anxe2x88x921 is shifted, and the output of the address buffer 12nxe2x88x921 initially corresponding to the address data bit Anxe2x88x921 is fixed. Nevertheless, it looks as if the address data value An was fixed.
Therefore, even if the defective memory cells occur in the areas designated by the address data value Anxe2x88x921=0 in the semiconductor memory, the semiconductor memory can be used as a memory having a memory capacity one half its original capacity without using the bin 11n at the highest hierarchical level.
Another exemplary semiconductor memory of the aforesaid type disclosed in Japanese Unexamined Patent Publication No. 2001-28198 is adapted to fix an address signal by fusing off a fuse. The semiconductor memory employs a circuit as shown in FIG. 8 for fixing address data at a logic xe2x80x9c0xe2x80x9d level or a logic xe2x80x9c1xe2x80x9d level.
In FIG. 8, there are shown an address pad (a) to which the address data is inputted, P-channel transistors (b) and (c), N-channel transistors (j), (k) and (g), and fuses (d), (e), (f), (h) and (i).
The address pad (a) is connected to an address buffer via the fuse (f). The P-channel transistor (b) has a gate connected to the ground GND, a source connected to a power supply voltage Vcc, and a drain connected to a drain of the N-channel transistor (j) via the fuses (d) and (h). The N-channel transistor (j) has a gate connected to the power supply voltage Vcc, and a source connected to the ground GND.
The P-channel transistor (c) has a gate connected to the ground GND, a source connected to the power supply voltage Vcc, and a drain connected to a drain of the N-channel transistor (k) via the fuses (e) and (i). The N-channel transistor (k) has a gate connected to the power supply voltage Vcc, and a source connected to the ground GND.
A reference character (A) denotes a node for interconnection between the P-channel transistor (b) and the N-channel transistor (j), and a reference character (B) denotes a node for interconnection between the P-channel transistor (c) and the N-channel transistor (k). The N-channel transistor (g) has a gate connected to the node (B), a source connected to the node (A), and a drain connected to the address buffer.
The P-channel transistors (b) and (c) and the N-channel transistors (j) and (k) are properly dimensioned so that potentials at the nodes (A) and (B) are set at the logic xe2x80x9c1xe2x80x9d level and the logic xe2x80x9c0xe2x80x9d level, respectively.
An explanation will be given to a case where the full memory capacity of the semiconductor memory is available for reading, i.e., bit data applied to the address pad is inputted as it is to the address buffer.
In this case, the polysilicon fuses (d), (h), (e), (i) are fused off. As a result, the input from the address pad (a) is inputted to the address buffer via the polysilicon fuse (f). Thus, the full memory capacity of the semiconductor memory is available for reading.
Next, an explanation will be given to a case where the input to the address buffer is fixed at the logic xe2x80x9c0xe2x80x9d level.
In this case, the fuse (f) is fused off by laser radiation or the like, so that the input from the address pad is prevented from being applied to the address buffer. Then, the potential at the node (A) is set at the logic xe2x80x9c0xe2x80x9d level by fusing off the fuse (d). Further, the potential at the node (B) is set at the logic xe2x80x9c1xe2x80x9d level by fusing off the fuse (i). Thus, the N-channel transistor (g) is turned on.
As a result, the potential (logic xe2x80x9c0xe2x80x9d level) at the node (A) is inputted as it is to the address buffer. Therefore, the input to the address buffer is fixed at the logic xe2x80x9c0xe2x80x9d level irrespective of the value of the address data.
Next, an explanation will be given to a case where the input to the address buffer is fixed at the logic xe2x80x9c1xe2x80x9d level.
In this case, the fuse (f) is fused off by laser radiation or the like so that the input from the address pad is prevented from being applied to the address buffer. Then, the potential at the node (A) is set at the logic xe2x80x9c1xe2x80x9d level by fusing off the fuse (h). Further, the potential at the node (B) is set at the logic xe2x80x9c1xe2x80x9d level by fusing off the fuse (i). Thus, the N-channel transistor (g) is turned on.
As a result, the potential (logic xe2x80x9c1xe2x80x9d level) at the node (A) is inputted as it is to the address buffer. Therefore, the input to the address buffer is fixed at the logic xe2x80x9c1xe2x80x9d level irrespective of the value of the address data.
In the case of the semiconductor memory disclosed in Japanese Unexamined Patent Publication No. SHO 59 (1984)-40392, however, the interconnection line 15 is kept at the logic xe2x80x9c1xe2x80x9d level by the MOSFETs 17, 18, and the interconnection line 16 is kept at the logic xe2x80x9c0xe2x80x9d level by the MOSFETs 19, 20. Where no defective memory cell is present in the memory areas, i.e., the full memory capacity is available, electric currents flow through the interconnection lines 15 and 16, so that the power is constantly consumed.
The semiconductor memory disclosed in Japanese Unexamined Patent Publication No. 2001-28198 is free from the wasteful power consumption by the interconnection lines, but requires the laser radiation for fusing off the fuses. Therefore, it is impossible to fix address data after the assembling to remedy a defective product.
In view of the foregoing, the present invention is directed to a semiconductor memory which is capable of controlling the passage, fixing and shifting of address data by means of a single circuit for prevention of wasteful power consumption thereof and, even if having a defective memory cell after the assembling thereof, can be used as an acceptable device having a smaller memory capacity than its original capacity without changing the positions of address input terminals.
The present invention provides a semiconductor memory having a plurality of memory cells, comprising: a plurality of address pads for receiving plural address data bits respectively inputted thereto for designating memory cell areas; a plurality of address buffers provided in one-to-one correspondence with the address pads for applying the address data bits to corresponding address decoders for selecting any of the memory cell areas; and a plurality of address input selection circuits respectively provided between the address pads and the address buffers; wherein the address input selection circuits each receive two control signals each having either an L-level or an H-level, an address data bit applied from a corresponding one of the address pads and an address data bit applied from an address pad at a one-bit lower hierarchical level than the corresponding address pad, then select one of a signal fixed at either the L-level or the H-level, a signal indicative of the address data bit applied from the corresponding address pad and a signal indicative of the address data bit applied from the address pad at the one-bit lower hierarchical level than the corresponding address pad on the basis of the levels of the two control signals, and output the selected signal to the corresponding address buffer.
According to the present invention, the address input selection circuit selects one of the signal fixed at either the L-level or the H-level, the signal indicative of the address data bit applied from the corresponding address pad and the signal indicative of the address data bit applied from the address pad at the one-bit lower hierarchical level than the corresponding address pad on the basis of the levels of the two control signals, and outputs the selected signal to the corresponding address buffer.
Therefore, where no defective memory cell is present in the semiconductor memory, the address data bit from the corresponding address pad can be outputted as it is to the corresponding address buffer by properly setting the levels of the two control signals to be inputted to the address input selection circuit.
Where a defective memory cell is present in an area of the semiconductor memory, an address data bit corresponding to the defective memory area can be fixed. In this case, an address input selection circuit at a lower hierarchical level than the address input selection circuit having the fixed bit can output an address data bit applied from the corresponding address pad to the corresponding address buffer on an xe2x80x9cas isxe2x80x9d basis. Further, an address input selection circuit at a higher hierarchical level than the address input selection circuit having the fixed bit can output an address data bit applied from an address pad at a one-bit lower hierarchical level than the corresponding address pad to the corresponding address buffer.
Even if a defective memory cell occurs in an area corresponding to any address data bit in the semiconductor memory after the assembling, the semiconductor memory can be used as an acceptable device having a smaller memory capacity than its original capacity without changing the positions of address input terminals. Thus, the semiconductor memory can be remedied. Further, the semiconductor memory is free from wasteful power consumption.